h8.h File Reference

Internal Interface: H8/3297 processor registers. More...

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Macros

#define TIER_ENABLE_ICA   0x80
 
#define TIER_ENABLE_ICB   0x40
 
#define TIER_ENABLE_ICC   0x20
 
#define TIER_ENABLE_ICD   0x10
 
#define TIER_ENABLE_OCA   0x08
 
#define TIER_ENABLE_OCB   0x04
 
#define TIER_ENABLE_OF   0x02
 
#define TIER_RESERVED   0x01
 
#define TCSR_ICA   0x80
 
#define TCSR_ICB   0x40
 
#define TCSR_ICC   0x20
 
#define TCSR_ICD   0x10
 
#define TCSR_OCA   0x08
 
#define TCSR_OCB   0x04
 
#define TCSR_OF   0x02
 
#define TCSR_RESET_ON_A   0x01
 
#define TCR_A_RISING   0x80
 
#define TCR_B_RISING   0x40
 
#define TCR_C_RISING   0x20
 
#define TCR_D_RISING   0x10
 
#define TCR_BUFFER_A   0x08
 
#define TCR_BUFFER_B   0x04
 
#define TCR_CLOCK_2   0x00
 
#define TCR_CLOCK_8   0x01
 
#define TCR_CLOCK_32   0x02
 
#define TCR_CLOCK_EXT   0x03
 
#define TOCR_OCRA   0x00
 
#define TOCR_OCRB   0x10
 
#define TOCR_ENABLE_A   0x08
 
#define TOCR_ENABLE_B   0x04
 
#define TOCR_HIGH_LEVEL_A   0x02
 
#define TOCR_HIGH_LEVEL_B   0x01
 
#define CR_ENABLE_IRQA   0x40
 
#define CR_ENABLE_IRQB   0x80
 
#define CR_ENABLE_IRQO   0x20
 
#define CR_CLEAR_NEVER   0x00
 
#define CR_CLEAR_ON_A   0x08
 
#define CR_CLEAR_ON_B   0x10
 
#define CR_CLEAR_ON_EXTERN   0x18
 
#define CSR_MATCH_A   0x40
 
#define CSR_MATCH_B   0x80
 
#define CSR_OVERFLOW   0x20
 
#define CSR_IGNORE_B   0x00
 
#define CSR_0_ON_B   0x04
 
#define CSR_1_ON_B   0x08
 
#define CSR_TOGGLE_ON_B   0x0c
 
#define CSR_IGNORE_A   0x00
 
#define CSR_0_ON_A   0x01
 
#define CSR_1_ON_A   0x02
 
#define CSR_TOGGLE_ON_A   0x03
 
#define SMR_SYNC   0x80
 
#define SMR_ASYNC   0x00
 
#define SMR_7BIT   0x40
 
#define SMR_8BIT   0x00
 
#define SMR_P_NONE   0x00
 
#define SMR_P_EVEN   0x20
 
#define SMR_P_ODD   0x30
 
#define SMR_1STOP   0x00
 
#define SMR_2STOP   0x08
 
#define SMR_MP   0x04
 
#define SMR_CLOCK   0x00
 
#define SMR_CLOCK_4   0x01
 
#define SMR_CLOCK_16   0x02
 
#define SMR_CLOCK_64   0x03
 
#define SCR_TX_IRQ   0x80
 
#define SCR_RX_IRQ   0x40
 
#define SCR_TRANSMIT   0x20
 
#define SCR_RECEIVE   0x10
 
#define SCR_MP_IRQ   0x08
 
#define SCR_TE_IRQ   0x04
 
#define SCR_INT_CLOCK   0x00
 
#define SCR_EXT_CLOCK   0x02
 
#define SCR_CLOCK_OUT   0x01
 
#define SSR_TRANS_EMPTY   0x80
 
#define SSR_RECV_FULL   0x40
 
#define SSR_OVERRUN_ERR   0x20
 
#define SSR_FRAMING_ERR   0x10
 
#define SSR_PARITY_ERR   0x08
 
#define SSR_ERRORS   0x38
 
#define SSR_TRANS_END   0x04
 
#define SSR_MP   0x02
 
#define SSR_MP_TRANSFER   0x01
 
#define B2400   207
 
#define B4800   103
 
#define B9600   51
 
#define B19200   25
 
#define B38400   12
 
#define ADCSR_END   0x80
 
#define ADCSR_ENABLE_IRQ   0x40
 
#define ADCSR_START   0x20
 
#define ADCSR_SCAN   0x10
 
#define ADCSR_TIME_266   0x00
 
#define ADCSR_TIME_134   0x08
 
#define ADCSR_GROUP_0   0x00
 
#define ADCSR_GROUP_1   0x04
 
#define ADCSR_AN_0   0x00
 
#define ADCSR_AN_1   0x01
 
#define ADCSR_AN_2   0x02
 
#define ADCSR_AN_3   0x03
 
#define ADCR_EXTERN   0x80
 
#define SYSCR_SOFTWARE_STANDBY   0x80
 
#define WDT_CSR_PASSWORD   (0xA500)
 
#define WDT_CSR_ENABLE   (0x0020)
 
#define WDT_CSR_MODE_WATCHDOG   (0x0040)
 
#define WDT_CSR_MODE_OVERFLOW   (0x0000)
 
#define WDT_CSR_WATCHDOG_NMI   (0x0000)
 
#define WDT_CSR_WATCHDOG_RES   (0x0008)
 
#define WDT_CSR_CLOCK_2   (0x0000)
 
#define WDT_CSR_CLOCK_32   (0x0001)
 
#define WDT_CSR_CLOCK_64   (0x0002)
 
#define WDT_CSR_CLOCK_128   (0x0003)
 
#define WDT_CSR_CLOCK_256   (0x0004)
 
#define WDT_CSR_CLOCK_512   (0x0005)
 
#define WDT_CSR_CLOCK_2048   (0x0006)
 
#define WDT_CSR_CLOCK_4096   (0x0007)
 
#define WDT_CNT_PASSWORD   (0x5A00)
 
#define WDT_CNT_CLEAR   (0x0000)
 
#define WDT_CNT_MSEC_64   (0x0006)
 

Variables

unsigned char T_IER
 16-bit timer interrupt enable register
 
volatile unsigned char T_CSR
 16-bit timer control / status register
 
volatile unsigned T_CNT
 16-bit timer count register
 
unsigned T_OCRA
 16-bit timer output compare register A
 
unsigned T_OCRB
 16-bit timer output compare register B
 
unsigned char T_CR
 16-bit timer control register
 
unsigned char T_OCR
 16-bit timer output control register
 
volatile unsigned T_ICRA
 16-bit timer input capture A register
 
volatile unsigned T_ICRB
 16-bit timer input capture B register
 
volatile unsigned T_ICRC
 16-bit timer input capture C register
 
volatile unsigned T_ICRD
 16-bit timer input capture D register
 
unsigned char STCR
 serial / timer control register
 
unsigned char T0_CR
 timer 0 control register
 
volatile unsigned char T0_CSR
 timer 0 control / status register
 
unsigned char T0_CORA
 timer 0 constant A register
 
unsigned char T0_CORB
 timer 0 constant B register
 
volatile unsigned char T0_CNT
 timer 0 counter register
 
unsigned char T1_CR
 timer 1 control register
 
volatile unsigned char T1_CSR
 timer 1 control / status register
 
unsigned char T1_CORA
 timer 1 constant A register
 
unsigned char T1_CORB
 timer 1 constant B register
 
volatile unsigned char T1_CNT
 timer 1 counter register
 
volatile unsigned char S_RDR
 serial receive data register
 
unsigned char S_TDR
 serial transmit data register
 
unsigned char S_MR
 serial mode register
 
unsigned char S_CR
 serial control register
 
volatile unsigned char S_SR
 serial status register
 
unsigned char S_BRR
 serial baud rate register
 
unsigned char S_TCR
 serial / timer control register
 
volatile unsigned char AD_A_H
 A/D converter data register A high.
 
volatile unsigned char AD_A_L
 A/D converter data register A low.
 
volatile unsigned char AD_B_H
 A/D converter data register B high.
 
volatile unsigned char AD_B_L
 A/D converter data register B low.
 
volatile unsigned char AD_C_H
 A/D converter data register C high.
 
volatile unsigned char AD_C_L
 A/D converter data register C low.
 
volatile unsigned char AD_D_H
 A/D converter data register D high.
 
volatile unsigned char AD_D_L
 A/D converter data register D low.
 
volatile unsigned AD_A
 A/D converter data register A.
 
volatile unsigned AD_B
 A/D converter data register B.
 
volatile unsigned AD_C
 A/D converter data register C.
 
volatile unsigned AD_D
 A/D converter data register D.
 
volatile unsigned char AD_CSR
 A/D converter control / status register.
 
unsigned char AD_CR
 A/D converter control register.
 
unsigned char SYSCR
 system control register
 
unsigned char PORT1_PCR
 port 1 input pull-up control register
 
unsigned char PORT2_PCR
 port 2 input pull-up control register
 
unsigned char PORT3_PCR
 port 3 input pull-up control register
 
unsigned char PORT1_DDR
 port 1 data direction register
 
volatile unsigned char PORT1
 port 1 I/O register
 
unsigned char PORT2_DDR
 port 2 data direction register
 
volatile unsigned char PORT2
 port 2 I/O register
 
unsigned char PORT3_DDR
 port 3 data direction register
 
volatile unsigned char PORT3
 port 3 I/O register
 
unsigned char PORT4_DDR
 port 4 data direction register
 
volatile unsigned char PORT4
 port 4 I/O register
 
unsigned char PORT5_DDR
 port 5 data direction register
 
volatile unsigned char PORT5
 port 5 I/O register
 
unsigned char PORT6_DDR
 port 6 data direction register
 
volatile unsigned char PORT6
 port 6 I/O register
 
volatile unsigned char PORT7
 port 7 input register
 
volatile unsigned int WDT_CSR
 watch dog timer control register
 
volatile unsigned char WDT_CNT
 watch dog timer counter register
 

Detailed Description

Internal Interface: H8/3297 processor registers.

Author
Markus L. Noga marku.nosp@m.s@no.nosp@m.ga.de

Definition in file h8.h.

Macro Definition Documentation

◆ ADCR_EXTERN

#define ADCR_EXTERN   0x80

Definition at line 351 of file h8.h.

◆ ADCSR_AN_0

#define ADCSR_AN_0   0x00

Definition at line 342 of file h8.h.

◆ ADCSR_AN_1

#define ADCSR_AN_1   0x01

Definition at line 343 of file h8.h.

◆ ADCSR_AN_2

#define ADCSR_AN_2   0x02

Definition at line 344 of file h8.h.

◆ ADCSR_AN_3

#define ADCSR_AN_3   0x03

Definition at line 345 of file h8.h.

◆ ADCSR_ENABLE_IRQ

#define ADCSR_ENABLE_IRQ   0x40

Definition at line 333 of file h8.h.

◆ ADCSR_END

#define ADCSR_END   0x80

Definition at line 332 of file h8.h.

◆ ADCSR_GROUP_0

#define ADCSR_GROUP_0   0x00

Definition at line 339 of file h8.h.

◆ ADCSR_GROUP_1

#define ADCSR_GROUP_1   0x04

Definition at line 340 of file h8.h.

◆ ADCSR_SCAN

#define ADCSR_SCAN   0x10

Definition at line 335 of file h8.h.

◆ ADCSR_START

#define ADCSR_START   0x20

Definition at line 334 of file h8.h.

◆ ADCSR_TIME_134

#define ADCSR_TIME_134   0x08

Definition at line 337 of file h8.h.

◆ ADCSR_TIME_266

#define ADCSR_TIME_266   0x00

Definition at line 336 of file h8.h.

◆ B19200

#define B19200   25

Definition at line 268 of file h8.h.

◆ B2400

#define B2400   207

Definition at line 265 of file h8.h.

◆ B38400

#define B38400   12

Definition at line 269 of file h8.h.

◆ B4800

#define B4800   103

Definition at line 266 of file h8.h.

◆ B9600

#define B9600   51

Definition at line 267 of file h8.h.

◆ CR_CLEAR_NEVER

#define CR_CLEAR_NEVER   0x00

Definition at line 166 of file h8.h.

◆ CR_CLEAR_ON_A

#define CR_CLEAR_ON_A   0x08

Definition at line 167 of file h8.h.

◆ CR_CLEAR_ON_B

#define CR_CLEAR_ON_B   0x10

Definition at line 168 of file h8.h.

◆ CR_CLEAR_ON_EXTERN

#define CR_CLEAR_ON_EXTERN   0x18

Definition at line 169 of file h8.h.

◆ CR_ENABLE_IRQA

#define CR_ENABLE_IRQA   0x40

Definition at line 162 of file h8.h.

◆ CR_ENABLE_IRQB

#define CR_ENABLE_IRQB   0x80

Definition at line 163 of file h8.h.

◆ CR_ENABLE_IRQO

#define CR_ENABLE_IRQO   0x20

Definition at line 164 of file h8.h.

◆ CSR_0_ON_A

#define CSR_0_ON_A   0x01

Definition at line 188 of file h8.h.

◆ CSR_0_ON_B

#define CSR_0_ON_B   0x04

Definition at line 183 of file h8.h.

◆ CSR_1_ON_A

#define CSR_1_ON_A   0x02

Definition at line 189 of file h8.h.

◆ CSR_1_ON_B

#define CSR_1_ON_B   0x08

Definition at line 184 of file h8.h.

◆ CSR_IGNORE_A

#define CSR_IGNORE_A   0x00

Definition at line 187 of file h8.h.

◆ CSR_IGNORE_B

#define CSR_IGNORE_B   0x00

Definition at line 182 of file h8.h.

◆ CSR_MATCH_A

#define CSR_MATCH_A   0x40

Definition at line 178 of file h8.h.

◆ CSR_MATCH_B

#define CSR_MATCH_B   0x80

Definition at line 179 of file h8.h.

◆ CSR_OVERFLOW

#define CSR_OVERFLOW   0x20

Definition at line 180 of file h8.h.

◆ CSR_TOGGLE_ON_A

#define CSR_TOGGLE_ON_A   0x03

Definition at line 190 of file h8.h.

◆ CSR_TOGGLE_ON_B

#define CSR_TOGGLE_ON_B   0x0c

Definition at line 185 of file h8.h.

◆ SCR_CLOCK_OUT

#define SCR_CLOCK_OUT   0x01

Definition at line 245 of file h8.h.

◆ SCR_EXT_CLOCK

#define SCR_EXT_CLOCK   0x02

Definition at line 244 of file h8.h.

◆ SCR_INT_CLOCK

#define SCR_INT_CLOCK   0x00

Definition at line 243 of file h8.h.

◆ SCR_MP_IRQ

#define SCR_MP_IRQ   0x08

Definition at line 241 of file h8.h.

◆ SCR_RECEIVE

#define SCR_RECEIVE   0x10

Definition at line 240 of file h8.h.

◆ SCR_RX_IRQ

#define SCR_RX_IRQ   0x40

Definition at line 238 of file h8.h.

◆ SCR_TE_IRQ

#define SCR_TE_IRQ   0x04

Definition at line 242 of file h8.h.

◆ SCR_TRANSMIT

#define SCR_TRANSMIT   0x20

Definition at line 239 of file h8.h.

◆ SCR_TX_IRQ

#define SCR_TX_IRQ   0x80

Definition at line 237 of file h8.h.

◆ SMR_1STOP

#define SMR_1STOP   0x00

Definition at line 227 of file h8.h.

◆ SMR_2STOP

#define SMR_2STOP   0x08

Definition at line 228 of file h8.h.

◆ SMR_7BIT

#define SMR_7BIT   0x40

Definition at line 222 of file h8.h.

◆ SMR_8BIT

#define SMR_8BIT   0x00

Definition at line 223 of file h8.h.

◆ SMR_ASYNC

#define SMR_ASYNC   0x00

Definition at line 221 of file h8.h.

◆ SMR_CLOCK

#define SMR_CLOCK   0x00

Definition at line 231 of file h8.h.

◆ SMR_CLOCK_16

#define SMR_CLOCK_16   0x02

Definition at line 233 of file h8.h.

◆ SMR_CLOCK_4

#define SMR_CLOCK_4   0x01

Definition at line 232 of file h8.h.

◆ SMR_CLOCK_64

#define SMR_CLOCK_64   0x03

Definition at line 234 of file h8.h.

◆ SMR_MP

#define SMR_MP   0x04

Definition at line 229 of file h8.h.

◆ SMR_P_EVEN

#define SMR_P_EVEN   0x20

Definition at line 225 of file h8.h.

◆ SMR_P_NONE

#define SMR_P_NONE   0x00

Definition at line 224 of file h8.h.

◆ SMR_P_ODD

#define SMR_P_ODD   0x30

Definition at line 226 of file h8.h.

◆ SMR_SYNC

#define SMR_SYNC   0x80

Definition at line 220 of file h8.h.

◆ SSR_ERRORS

#define SSR_ERRORS   0x38

Definition at line 253 of file h8.h.

◆ SSR_FRAMING_ERR

#define SSR_FRAMING_ERR   0x10

Definition at line 251 of file h8.h.

◆ SSR_MP

#define SSR_MP   0x02

Definition at line 255 of file h8.h.

◆ SSR_MP_TRANSFER

#define SSR_MP_TRANSFER   0x01

Definition at line 256 of file h8.h.

◆ SSR_OVERRUN_ERR

#define SSR_OVERRUN_ERR   0x20

Definition at line 250 of file h8.h.

◆ SSR_PARITY_ERR

#define SSR_PARITY_ERR   0x08

Definition at line 252 of file h8.h.

◆ SSR_RECV_FULL

#define SSR_RECV_FULL   0x40

Definition at line 249 of file h8.h.

◆ SSR_TRANS_EMPTY

#define SSR_TRANS_EMPTY   0x80

Definition at line 248 of file h8.h.

◆ SSR_TRANS_END

#define SSR_TRANS_END   0x04

Definition at line 254 of file h8.h.

◆ SYSCR_SOFTWARE_STANDBY

#define SYSCR_SOFTWARE_STANDBY   0x80

Definition at line 361 of file h8.h.

◆ TCR_A_RISING

#define TCR_A_RISING   0x80

Definition at line 98 of file h8.h.

◆ TCR_B_RISING

#define TCR_B_RISING   0x40

Definition at line 99 of file h8.h.

◆ TCR_BUFFER_A

#define TCR_BUFFER_A   0x08

Definition at line 102 of file h8.h.

◆ TCR_BUFFER_B

#define TCR_BUFFER_B   0x04

Definition at line 103 of file h8.h.

◆ TCR_C_RISING

#define TCR_C_RISING   0x20

Definition at line 100 of file h8.h.

◆ TCR_CLOCK_2

#define TCR_CLOCK_2   0x00

Definition at line 104 of file h8.h.

◆ TCR_CLOCK_32

#define TCR_CLOCK_32   0x02

Definition at line 106 of file h8.h.

◆ TCR_CLOCK_8

#define TCR_CLOCK_8   0x01

Definition at line 105 of file h8.h.

◆ TCR_CLOCK_EXT

#define TCR_CLOCK_EXT   0x03

Definition at line 107 of file h8.h.

◆ TCR_D_RISING

#define TCR_D_RISING   0x10

Definition at line 101 of file h8.h.

◆ TCSR_ICA

#define TCSR_ICA   0x80

Definition at line 86 of file h8.h.

◆ TCSR_ICB

#define TCSR_ICB   0x40

Definition at line 87 of file h8.h.

◆ TCSR_ICC

#define TCSR_ICC   0x20

Definition at line 88 of file h8.h.

◆ TCSR_ICD

#define TCSR_ICD   0x10

Definition at line 89 of file h8.h.

◆ TCSR_OCA

#define TCSR_OCA   0x08

Definition at line 90 of file h8.h.

◆ TCSR_OCB

#define TCSR_OCB   0x04

Definition at line 91 of file h8.h.

◆ TCSR_OF

#define TCSR_OF   0x02

Definition at line 92 of file h8.h.

◆ TCSR_RESET_ON_A

#define TCSR_RESET_ON_A   0x01

Definition at line 93 of file h8.h.

◆ TIER_ENABLE_ICA

#define TIER_ENABLE_ICA   0x80

Definition at line 74 of file h8.h.

◆ TIER_ENABLE_ICB

#define TIER_ENABLE_ICB   0x40

Definition at line 75 of file h8.h.

◆ TIER_ENABLE_ICC

#define TIER_ENABLE_ICC   0x20

Definition at line 76 of file h8.h.

◆ TIER_ENABLE_ICD

#define TIER_ENABLE_ICD   0x10

Definition at line 77 of file h8.h.

◆ TIER_ENABLE_OCA

#define TIER_ENABLE_OCA   0x08

Definition at line 78 of file h8.h.

◆ TIER_ENABLE_OCB

#define TIER_ENABLE_OCB   0x04

Definition at line 79 of file h8.h.

◆ TIER_ENABLE_OF

#define TIER_ENABLE_OF   0x02

Definition at line 80 of file h8.h.

◆ TIER_RESERVED

#define TIER_RESERVED   0x01

Definition at line 81 of file h8.h.

◆ TOCR_ENABLE_A

#define TOCR_ENABLE_A   0x08

Definition at line 114 of file h8.h.

◆ TOCR_ENABLE_B

#define TOCR_ENABLE_B   0x04

Definition at line 115 of file h8.h.

◆ TOCR_HIGH_LEVEL_A

#define TOCR_HIGH_LEVEL_A   0x02

Definition at line 116 of file h8.h.

◆ TOCR_HIGH_LEVEL_B

#define TOCR_HIGH_LEVEL_B   0x01

Definition at line 117 of file h8.h.

◆ TOCR_OCRA

#define TOCR_OCRA   0x00

Definition at line 112 of file h8.h.

◆ TOCR_OCRB

#define TOCR_OCRB   0x10

Definition at line 113 of file h8.h.

◆ WDT_CNT_CLEAR

#define WDT_CNT_CLEAR   (0x0000)

Definition at line 447 of file h8.h.

◆ WDT_CNT_MSEC_64

#define WDT_CNT_MSEC_64   (0x0006)

Definition at line 448 of file h8.h.

◆ WDT_CNT_PASSWORD

#define WDT_CNT_PASSWORD   (0x5A00)

Definition at line 446 of file h8.h.

◆ WDT_CSR_CLOCK_128

#define WDT_CSR_CLOCK_128   (0x0003)

Definition at line 437 of file h8.h.

◆ WDT_CSR_CLOCK_2

#define WDT_CSR_CLOCK_2   (0x0000)

Definition at line 434 of file h8.h.

◆ WDT_CSR_CLOCK_2048

#define WDT_CSR_CLOCK_2048   (0x0006)

Definition at line 440 of file h8.h.

◆ WDT_CSR_CLOCK_256

#define WDT_CSR_CLOCK_256   (0x0004)

Definition at line 438 of file h8.h.

◆ WDT_CSR_CLOCK_32

#define WDT_CSR_CLOCK_32   (0x0001)

Definition at line 435 of file h8.h.

◆ WDT_CSR_CLOCK_4096

#define WDT_CSR_CLOCK_4096   (0x0007)

Definition at line 441 of file h8.h.

◆ WDT_CSR_CLOCK_512

#define WDT_CSR_CLOCK_512   (0x0005)

Definition at line 439 of file h8.h.

◆ WDT_CSR_CLOCK_64

#define WDT_CSR_CLOCK_64   (0x0002)

Definition at line 436 of file h8.h.

◆ WDT_CSR_ENABLE

#define WDT_CSR_ENABLE   (0x0020)

Definition at line 429 of file h8.h.

◆ WDT_CSR_MODE_OVERFLOW

#define WDT_CSR_MODE_OVERFLOW   (0x0000)

Definition at line 431 of file h8.h.

◆ WDT_CSR_MODE_WATCHDOG

#define WDT_CSR_MODE_WATCHDOG   (0x0040)

Definition at line 430 of file h8.h.

◆ WDT_CSR_PASSWORD

#define WDT_CSR_PASSWORD   (0xA500)

Definition at line 428 of file h8.h.

◆ WDT_CSR_WATCHDOG_NMI

#define WDT_CSR_WATCHDOG_NMI   (0x0000)

Definition at line 432 of file h8.h.

◆ WDT_CSR_WATCHDOG_RES

#define WDT_CSR_WATCHDOG_RES   (0x0008)

Definition at line 433 of file h8.h.

Variable Documentation

◆ AD_A

volatile unsigned AD_A
extern

A/D converter data register A.

bits 0..5 reserved, probably zero

◆ AD_A_H

volatile unsigned char AD_A_H
extern

A/D converter data register A high.

◆ AD_A_L

volatile unsigned char AD_A_L
extern

A/D converter data register A low.

bits 0..5 reserved, probably zero

◆ AD_B

volatile unsigned AD_B
extern

A/D converter data register B.

bits 0..5 reserved, probably zero

◆ AD_B_H

volatile unsigned char AD_B_H
extern

A/D converter data register B high.

◆ AD_B_L

volatile unsigned char AD_B_L
extern

A/D converter data register B low.

bits 0..5 reserved, probably zero

◆ AD_C

volatile unsigned AD_C
extern

A/D converter data register C.

bits 0..5 reserved, probably zero

◆ AD_C_H

volatile unsigned char AD_C_H
extern

A/D converter data register C high.

◆ AD_C_L

volatile unsigned char AD_C_L
extern

A/D converter data register C low.

bits 0..5 reserved, probably zero

◆ AD_CR

unsigned char AD_CR
extern

A/D converter control register.

◆ AD_CSR

volatile unsigned char AD_CSR
extern

A/D converter control / status register.

◆ AD_D

volatile unsigned AD_D
extern

A/D converter data register D.

bits 0..5 reserved, probably zero

◆ AD_D_H

volatile unsigned char AD_D_H
extern

A/D converter data register D high.

◆ AD_D_L

volatile unsigned char AD_D_L
extern

A/D converter data register D low.

bits 0..5 reserved, probably zero

◆ PORT1

volatile unsigned char PORT1
extern

port 1 I/O register

◆ PORT1_DDR

unsigned char PORT1_DDR
extern

port 1 data direction register

◆ PORT1_PCR

unsigned char PORT1_PCR
extern

port 1 input pull-up control register

◆ PORT2

volatile unsigned char PORT2
extern

port 2 I/O register

◆ PORT2_DDR

unsigned char PORT2_DDR
extern

port 2 data direction register

◆ PORT2_PCR

unsigned char PORT2_PCR
extern

port 2 input pull-up control register

◆ PORT3

volatile unsigned char PORT3
extern

port 3 I/O register

◆ PORT3_DDR

unsigned char PORT3_DDR
extern

port 3 data direction register

◆ PORT3_PCR

unsigned char PORT3_PCR
extern

port 3 input pull-up control register

◆ PORT4

volatile unsigned char PORT4
extern

port 4 I/O register

Referenced by lnp_logical_range(), and lnp_logical_range_is_far().

◆ PORT4_DDR

unsigned char PORT4_DDR
extern

port 4 data direction register

◆ PORT5

volatile unsigned char PORT5
extern

port 5 I/O register

◆ PORT5_DDR

unsigned char PORT5_DDR
extern

port 5 data direction register

◆ PORT6

volatile unsigned char PORT6
extern

port 6 I/O register

Referenced by ds_passive().

◆ PORT6_DDR

unsigned char PORT6_DDR
extern

port 6 data direction register

Referenced by i2c_read_ack(), and lcd_init().

◆ PORT7

volatile unsigned char PORT7
extern

port 7 input register

◆ S_BRR

unsigned char S_BRR
extern

serial baud rate register

◆ S_CR

unsigned char S_CR
extern

serial control register

◆ S_MR

unsigned char S_MR
extern

serial mode register

◆ S_RDR

volatile unsigned char S_RDR
extern

serial receive data register

◆ S_SR

volatile unsigned char S_SR
extern

serial status register

◆ S_TCR

unsigned char S_TCR
extern

serial / timer control register

◆ S_TDR

unsigned char S_TDR
extern

serial transmit data register

◆ STCR

unsigned char STCR
extern

serial / timer control register

◆ SYSCR

unsigned char SYSCR
extern

system control register

◆ T0_CNT

volatile unsigned char T0_CNT
extern

timer 0 counter register

◆ T0_CORA

unsigned char T0_CORA
extern

timer 0 constant A register

◆ T0_CORB

unsigned char T0_CORB
extern

timer 0 constant B register

◆ T0_CR

unsigned char T0_CR
extern

timer 0 control register

◆ T0_CSR

volatile unsigned char T0_CSR
extern

timer 0 control / status register

◆ T1_CNT

volatile unsigned char T1_CNT
extern

timer 1 counter register

◆ T1_CORA

unsigned char T1_CORA
extern

timer 1 constant A register

◆ T1_CORB

unsigned char T1_CORB
extern

timer 1 constant B register

◆ T1_CR

unsigned char T1_CR
extern

timer 1 control register

◆ T1_CSR

volatile unsigned char T1_CSR
extern

timer 1 control / status register

◆ T_CNT

volatile unsigned T_CNT
extern

16-bit timer count register

◆ T_CR

unsigned char T_CR
extern

16-bit timer control register

Referenced by systime_init().

◆ T_CSR

volatile unsigned char T_CSR
extern

16-bit timer control / status register

Referenced by systime_init().

◆ T_ICRA

volatile unsigned T_ICRA
extern

16-bit timer input capture A register

◆ T_ICRB

volatile unsigned T_ICRB
extern

16-bit timer input capture B register

◆ T_ICRC

volatile unsigned T_ICRC
extern

16-bit timer input capture C register

◆ T_ICRD

volatile unsigned T_ICRD
extern

16-bit timer input capture D register

◆ T_IER

unsigned char T_IER
extern

16-bit timer interrupt enable register

Referenced by systime_init(), and systime_shutdown().

◆ T_OCR

unsigned char T_OCR
extern

16-bit timer output control register

Referenced by systime_init().

◆ T_OCRA

unsigned T_OCRA
extern

16-bit timer output compare register A

Referenced by systime_init().

◆ T_OCRB

unsigned T_OCRB
extern

16-bit timer output compare register B

Referenced by systime_init().

◆ WDT_CNT

volatile unsigned char WDT_CNT
extern

watch dog timer counter register

◆ WDT_CSR

volatile unsigned int WDT_CSR
extern

watch dog timer control register

Referenced by systime_init(), and systime_shutdown().


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Original code copyright 1998-2005 by the authors.

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